The present application relates to semiconductor technology and more particularly to a method of forming tensily strained silicon fins in an nFET device region and compressively strained silicon germanium alloy (SiGe) fins in a pFET device region. The present application also relates to a semiconductor structure containing tensily strained silicon fins in an nFET device region and compressively strained silicon germanium alloy (SiGe) fins in a pFET device region.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
For FinFET performance increase, a strained channel material is needed. For CMOS devices, tensile strained silicon fins are beneficial for nFET devices, but not for pFET devices. Therefore, there is a need to release tensile strain in the pFET fins and also to add compressive strain to the pFET fins for further device performance enhancement.